This invention relates to a nonvolatile semiconductor memory device such as an electrically erasable and programmable read-only memory (EEPROM) having the ability to correct bit errors resulting from the degradation of memory cells, and to a microcomputer incorporating such a memory device.
Nonvolatile semiconductor memories are used for storing data on a permanent or semipermanent basis in a wide range of electronic devices including computers, computer peripheral equipment, office equipment, game machines, and IC cards. Although highly reliable, these nonvolatile semiconductor memories are not entirely free of bit errors caused by degradation of their constituent memory cells. In particular, EEPROM memories inevitably suffer degradation if they are reprogrammed frequently. The reliability of a nonvolatile semiconductor memory device can obviously be enhanced if the device is able to detect and correct its own bit errors.
One prior-art scheme for self-correction bit errors, described in an article on a 1M-bit masked ROM on pages 195 to 210 in Nikkei Electronics, September 26, 1983, makes use of a Hamming error-correcting code. Data are stored in words consisting of 2.sup.N bits each, and N+1 "parity bits" (error-correcting bits) are also stored for each word. For example, to store a four-bit data word (N=2), seven bits are used: the four data bits and three parity bits. The redundancy provided by the parity bits enables arbitrary one-bit errors to be detected and the bit in error to be identified. The memory device is constructed with AND and NOR gates that automatically check each word as it is read, detect any one-bit errors, and correct the value of the error bit in the output. Errors in more than one bit at a time cannot be reliably corrected by this scheme.
A similar scheme can be employed in a single-chip microcomputer comprising a central processing unit, input/output circuits, and memory on a semiconductor chip. The memory stores data in 2.sup.N -bit words, with (N+1) additional parity bits for each word. An error-correcting-code (ECC) circuit is interposed between the memory and the data bus. When data are written in the memory, the ECC circuit generates the necessary parity bits and supplies these together with the data bits to the memory. When data are read from the memory, the ECC circuit checks the data and parity bits, detects and corrects any one-bit errors, and places the correct data on the data bus.
A major drawback of these prior-art error-correcting schemes is the large number of extra bits required. The widely-used eight-bit word format, for example, requires four parity bits per word; error-correcting by this scheme increases the total number of bits that must be stored by a factor of 1.5. The size of the memory cell array must therefore be increased by a factor of 1.5, and still further space is required for the error-correction circuitry. Error correcting by this scheme thus exacts a high penalty in terms of chip area, necessitating larger chips. One unfortunate consequence of this is reduced yield of the fabrication process, because there are fewer chips per wafer. As noted in the reference cited above, the reduction in yield due to chip size tends to offset any gain in yield realized through the correction of bit errors. A low yield translates into a high cost per chip.
In single-chip microcomputers employing this error-correcting scheme, the increased size of the memory cell array places particularly severe constraints on the space left for other on-chip facilities, and the complexity of the error-correcting-code circuit complicates the chip design.